1. Field of the Invention
The present invention relates to data pipeline devices and to methods and circuits for generating control signals for data pipelines.
2. Description of the Prior Art
Synchronous Dynamic Random Access Memory (SDRAM) devices commonly include a data pipeline that a plurality of registers divides into stages. The latency or total transmission time of the data pipeline typically controls the access time of the SDRAM. Accordingly, the access time depends on the timing of pipeline control signals that operate the pipeline registers. In the conventional structure, an internal pipeline control signal generator generates the pipeline control signals from a reference clock signal. Typically, the data pipeline cannot be divided into stages having equal transmission times. Accordingly, the reference clock and the pipeline control signals have a period that is longer than the longest transmission time of any stage in the data pipeline.
The pipeline control signal generator generates the pipeline control signals via delay circuits, each having a different delay time. The delay time of each delay circuit includes a margin for variations in the timing of pipeline control signals. The margin accounts for expected variations in operating temperature and power supply voltage. Further, the margin at each stage is an accumulation of the margins for previous stages because each of the following stages of the data pipeline must accommodate what came before. The accumulated margins increase the latency of the data pipeline and reduce performance in applications such as SDRAM.
An aspect of the present invention is to provide high-speed pipeline devices and methods and circuits for generating control signals for data pipelines. In particular, embodiments of the present invention can minimize the required margins in multi-phase clock signals by generating the multi-phase clock signals in cascade.
According to the above aspect, a device in accordance with an exemplary embodiment of the present invention has n data pipeline stages with respective transmission times (T1, . . . , Tn). Each transmission time T1, . . . , Tn is shorter than the period P of a reference clock signal. At least one of the transmission times differs from another of the transmission times. The device includes n (n is a natural number) data path circuits or stages, n registers, and a control signal generating circuit. The data path circuits are connected in cascade between an input terminal and an output terminal. The registers connect to input terminals of respective data path circuits and latch data passed from a previous stage or the input terminal. The control signal generating circuit generates a first pipeline control signal in response to the reference clock signal, and other pipeline control signals in cascade from other pipeline control signals. The control signal generating circuit provides the n pipe registers with the n pipeline control signals. Accordingly, the total transmission time of data from the input terminal to the output terminal is about equal to the sum of the transmission times.
In one embodiment of the present invention, the control signal generating circuit includes a first pulse generator and a second pulse generator. The first pulse generator generates an (n)th pipeline control signal that is delayed relative to the reference clock signal, and the second pulse generator generates an (nxe2x88x921)th pipeline control signal by delaying the (n)th pipeline control. signal. The second pulse generator typically has an associated delay circuit that controls the delay of the (nxe2x88x921)th pipeline control signal. Additional pulse generators and delay circuits can be connected in a descending series and in cascade to generate further pipeline control signals by delaying other pipeline control signals.
According to another embodiment of the present invention, the control signal generating circuit includes a first pulse generator that inputs the reference clock signal and produces an (n)th pipeline control signal having pulses with a pulse width w1. A second pulse generator produces an (nxe2x88x921)th pipeline control signal having pulses with a pulse width w2 in response to trailing edges of active regions of the (n)th pipeline control signal.
A method according to an embodiment of the present invention includes generating a pipeline control signal having pulses delayed relative to transitions in a reference signal and generating another pipeline control signal by delaying the other pipeline control signal. The method may further include generating a plurality of pipeline control signals, wherein each pipeline control signal is generated by delaying another pipeline control signal. Active regions of each pipeline control signal can be synchronized with either the leading or trailing edges of the active regions of another of the control signals.